1. Field
Example embodiments of the present inventive concepts relate to semiconductor devices and methods for manufacturing the same.
2. Description of the Related Art
As a packaging technology of a semiconductor integrated circuit, a three-dimensional (3D) multilayer technology can heighten packaging density while reducing the size of an electronic element and can improve the performance of the semiconductor integrated circuit. A package using such a 3D multilayer technology is a package in which a plurality of chips having the same storage capacity are stacked, and is generally called a stack package. In the stack package, the data storage capacity can be easily increased, but the stack package has insufficient wiring space for electrical connections in the package as the number of stacked chips and the size thereof are increased.
Due to the insufficient wiring space in the stack package, a structure using a through silicon via (TSV) has been proposed, and recently, a method has been used to form a through electrode that is made of a conductive material in a semiconductor chip and to electrically connect semiconductor chips through the through electrode.
If the through electrode is used, it is possible to bond fine pitch I/O pads to cause the number of I/O pads to be increased, to improve the signal transfer speed between the chips through forming of the plurality of I/O pads, and to perform 3D design of the semiconductor chip to cause the performance of the semiconductor chip itself to be further improved.
On the other hand, the through silicon via (TSV) is formed through via first, via middle, and via last processes, which are classified depending on when the via is formed. Here, the “via last process” is general terminology for methods for forming via in a wafer state where the wafer fabrication has been completed, and the via last process is further divided into two processes: via last from frontside and via last from backside.
The via last from backside has mainly been used because it can reduce a via pitch, and has a simple process at low cost and high degrees of freedom.
However, a mask pattern for forming the via is formed on the back side of the wafer during the via last from backside, and in this case, misalignment may occur between a wafer backside portion that is exposed by the mask pattern and a pad that is formed on the frontside portion of the wafer. If such misalignment occurs, the via that is formed from the backside of the wafer is unable to be formed to expose the pad that is formed on the frontside of the waver, and as a result, the through electrode that is formed in the via is unable to be electrically connected to the semiconductor chip.